The present invention is related in general to the field of semiconductor devices and processes and more specifically to the fabrication of integrated circuit chips protected against potential damage caused by the propagation of cracks initiated by the step of separating semiconductor wafers into individual chips.
With most semiconductor products, for example integrated circuits, transistors and diodes, a large number of elements are manufactured simultaneously on a large semiconductor wafer of silicon, silicon germanium, gallium arsenide, etc. The semiconductor industry employs the terms xe2x80x9cdicing technologiesxe2x80x9d or xe2x80x9cscribing technologiesxe2x80x9d to refer to those techniques for obtaining a large number of functional chips, or dies, from each semiconductor wafer. Two dicing methods are particularly well known in the art: The grinding-cutting method, using a blade or wire saw, and the scribing method, using a diamond point. Modern silicon technology prefers the cutting method using high-speed rotating blades. When laying out the pattern of integrated circuit (IC) chips on the surface of the semiconductor wafer, manufacturing efficiency requires to minimize the distance between adjacent IC chips so that the number of obtainable chips (the production yield) can be maximized.
The technology of dicing has been developed to a high standard. In U.S. Pat. No. 4,610,079 of Sep. 9, 1986 (Abe et al., xe2x80x9cMethod of Dicing a Semiconductor Waferxe2x80x9d), it has been pointed out that three restrictions exist with respect to the minimum distance permissible between adjacent chips. The first restriction is the actual dicing width, the second restriction is the degree of precision to which the cutting machine can be adjusted, and the third restriction is the cracks and chip-outs extending laterally from the dicing line into the semiconductor and insulating materials. Even today, the third of these restrictions, namely the generation of cracks, creates significant limitations with respect to minimizing the distance between adjacent IC chips. In addition, those cracks represent significant reliability risks, since they tend to grow and widen under thermal and mechanical stress and thus eventually imperil the functionality of the IC.
Several solutions have been proposed to solve some of these technical problems associated with the manufacture and dicing of semiconductor wafers. The sealing of dicing streets against penetration of mobile ions with the help of metal edge barriers overlapping insulating layers was proposed in U.S. Pat. No. 4,364,078 of December 1982 (Smith et al., xe2x80x9cEdge Barrier of Polysilicon and Metal for Integrated Circuit Chipsxe2x80x9d) and U.S. Pat. No. 4,656,055 of April 1987 (Dwyer, xe2x80x9cDouble Level Metal Edge Seal for a Semiconductor Devicexe2x80x9d). These structures proved ineffective against cracks when insulators extend into the dicing lines and are subject to cracks during the dicing process. In U.S. Pat. No. 5,024,970 of June 1991 (Mori, xe2x80x9cMethod of Obtaining Semiconductor Chipsxe2x80x9d), small grooves are obtained in the insulating zone by plasma etching. Many cracks originating from the dicing process are seen to stop at these grooves, but not all of them.
Forming consecutive grooves of different widths by using diamond and resin blades has been described in U.S. Pat. No. 5,266,528 of November 1993 (Yamada et al., xe2x80x9cMethod of Dicing Semiconductor Wafer with Diamond and Resin Bladesxe2x80x9d). Dicing line features to limit the spreading of cracks and chip-outs generated during dicing have been proposed in U.S. Pat. No. 4,610,079 of September 1986, mentioned above. Avoiding residues of layers of non-uniform thicknesses, or the generation of lose particles, has been described in U.S. Pat. No. 5,136,354 of August 1992 (Morita et al., xe2x80x9cSemiconductor Device Wafer with Interlayer Insulating Film Covering the Scribe Linesxe2x80x9d) with added division in U.S. Pat. No. 5,237,199 of August 1993. In these patents, the etching of slit grooves in passivation films is described in order to stop cracks in the passivation layers during the dicing process.
The latter ideas were continued and elaborated in U.S. Pat. No. 5,414,297 of May 1995 (Morita et al., xe2x80x9cSemiconductor Device Chip with Interlayer Insulating Film Covering the Scribe Linesxe2x80x9d). In particular, it is described how the processes used in forming the conductive interconnections between elements of the integrated circuit can be exploited to generate one vertical metal line parallel to the dicing lines so that it extends around the entire periphery of each integrated circuit chip.
Practical semiconductor manufacturing has demonstrated, however, that these structures do not stop severe cracks originating in the dicing process. On the contrary, thermomechanical stresses generated by modern device applications, board attach processes, or rigorous environmental testing procedures may convey enough energy to many cracks so that they will eventually bypass obstacles or break through a single seal. Following these cracks, moisture and contamination are free to penetrate active circuitry and to start degrading the electrical device performance drastically.
In U.S. patent application Ser. No. 60/073,939, filed on Feb. 6, 1998 (Ibnabdeljalil et al, xe2x80x9cSacrificial Structures for Arresting Insulator Cracks in Semiconductor Devicesxe2x80x9d), scribe street seals are described having at least two sets of substantially parallel structures, each set extending along the edge of a chip on opposite sides of each dicing line. Each set comprises at least one continuous barrier wall and a sacrificial composite structure having means of dispersing the energy associated with crack propagation. This concept, however, does not prevent the lateral propagation of surface-near cracks or the risk of widespread delamination of structures especially when copper instead of aluminum is employed as interconnecting metal.
In summary, the goal of providing a technology for dicing semiconductor wafers with assured protection against mechanical and environmental damages and thus offering for the commercial and military markets cost-effective and reliable semiconductor products, manufactured in high volume and with flexible, low-cost design and production methods, has remained elusive, until now. The new design and method of fabrication should be flexible enough to be applied for different semiconductor product families and a wide spectrum of process variations. Preferably, these innovations should be accomplished using the installed equipment base so that no investment in new manufacturing machines is needed.
The invention describes sets of seal structures in semiconductor wafer scribe streets, extending along the edges of each integrated circuit chip and comprising a continuous barrier wall, adjacent to each chip, and a sacrificial composite structure, substantially parallel to the wall, being a discontinuous barrier wall comprising metal rivets interconnecting electrically conductive layers in an alternating pattern, and further describes slots opened into the protective overcoat of the wafer, reaching from the surface of the overcoat to the surface-nearest electrically conductive layer of the composite structure.
According to the Griffith energy-balance concept for crack formation in brittle solids (first published in 1920), a change in the length of a nascent crack or notch cannot change the sum of all energies; in other words, the sum of surface energy and mechanical energy has to stay constant. This means for a crack extension that the surface energy may generally increase, but the mechanical energy has to decrease. The mechanical energy itself consists of the sum of the strain potential energy stored in the material and the potential energy of the outer applied loading system. This says, whenever any of these energies can assume a lower value, the freed energy can be invested in generating more surface for an expanding crack.
Applying the Griffith equilibrium requirement to semiconductor devices, whenever uniform stress is applied (for instance during operation or testing of the semiconductor device) so that it is larger than the failure stress, a nascent crack may propagate spontaneously and without limitxe2x80x94unless it is stopped or arrested. The failure stress at the crack front, in turn, is proportional to the free surface energy per unit area and to Young""s modulus (a material constant), and inverse proportional to the length of the starter crack or notch. Since dicing streets are well-known areas for the generation of microcracks, they are prime concerns for latent failures of the semiconductor device due to propagating cracks.
The present invention comprises sacrificial structures for arresting insulator cracks in semiconductor circuit chips and methods for fabricating reinforced insulators in semiconductor wafers. It has particular application to dicing multilevel metal semiconductor wafers into individual circuit chips. The invention permits the introduction of electrically advantageous, but mechanically brittle insulators into the production of large-area, high-speed integrated circuits without risking reliability degradation through propagating cracks initiated by the dicing process.
Based on the invention, the fabrication of more than one metallic sacrificial structure transforms the brittle insulator areas around each circuit chip into reinforced composites with considerable toughness against fracture and propagation of nascent cracks. The main contribution to this toughness comes from the intrinsic adhesion energies of the components. The toughening is attributable to shielding processes, notably bridging, where the reinforcing phases are left intact as ligaments at the crack interface. Key to attaining effective toughening is the existence of suitably weak interfaces to allow debonding between the insulators and the reinforcing metal structures, and energy dissipation within the ensuing bridges at separation. Even without optimizing the shielding processes, large increases in peak stress and strain to failure have been observed, with the crack resistance energy per unit area increasing up to an order of magnitude.
If a crack were able to penetrate the first seal structure by breaking through a weak flaw, or due to rupturing of the metal seal structure, it would loose its energy in debonding due to the reinforced composite properties of the insulating area, and would be arrested by the next seal structure. With these structures, the brittle oxides can preserve their stiffness, but the metal structures enhance toughness and energy absorption capacity (illustrated by A. G. Evans, xe2x80x9cPerspective on the development of high-toughness ceramicsxe2x80x9d, J. Amer. Ceram. Soc., vol. 73, p. 187, 1990). If no full-scale plastic zone develops about the crack tip, the shielding is predominantly associated with dissociation of plastic energy at the metal across the crack interface.
The present invention is related to high density ICs, especially those having high numbers of inputs/outputs, and also to low end, low cost devices. These ICs can be found in many semiconductor device families such as standard linear and logic products, digital signal processors, microprocessors, digital and analog devices, high frequency and high power devices, and both large and small area chip categories. The present invention further meets the requirements for minimizing the sacrifice of semiconductor material for dicing. The package type can be plastic dual in-line packages (PDIPs), small outline ICs (SOICs), quad flat packs QFPs), thin QFPs (TQFPs), SSOPS, TSSOPS, TVSOPS, and other leadframe-based packages.
It is an object of the present invention to securely arrest any cracks originating from chip-outs caused by the rotating dicing blades, especially in the surface-near protective overcoat.
Another object of the present invention to provide reliability assurance for the finished product against mechanical stresses by introducing structural reinforcement of intermetal dielectrics, which also double as sealing barriers against migrating chemical impurities.
Another object of the present invention is to prevent delamination of dielectrics from copper metallization by designing the sacrificial structure in the scribe street as reinforcing rivets.
Another object of the present invention is to provide reliability assurance for the finished product by changing the failure mechanism from a probabilistic weakest-link mode to a parallel-type mode, effectively eliminating the failure mechanism. This built-in reliability assurance can be applied for several future generations of products.
Another object of the present invention is to apply electrical bias to at least some of the structures such as to arrest the drift of unwanted charged particles.
Another object of the present invention is to introduce a multitude of sacrificial structures such that they can be produced along with the integrated circuits without needing extra space or adding extra manufacturing cost.
These objects have been achieved by the design and mass production process of the sacrificial structures of the invention. Various modifications have been successfully employed for integrated circuits of different design rules and hierarchies of metal/insulator layer sequences.
In the first embodiment of the invention, metal-filled trenches are positioned on top of each other, forming a continuous xe2x80x9cwallxe2x80x9d of metal, which transects the layers of insulating films disposed on top of each other. Such metal wall, substantially parallel to the dicing lines, extends all around the periphery of the circuit chip and represents a sacrificial structure for protecting the chip circuitry.
For an insulator crack, originating at the dicing line and driven to propagate into the chip towards the integrated circuitry, a sacrificial structure consisting of metal rivets through the insulating layers and interconnecting electrically conductive layers in an alternating pattern, arrests further propagation by changing the failure mechanism from a probabilistic weakest-link mode to a parallel-type mode.
In an additional embodiment of the invention, the sacrificial structure is in electrical contact with a highly doped region of the semiconductor wafer. Electrical potential, such as ground potential, can thus be applied to the sacrificial structure, effectively stopping the drift of unwanted charged particles.
In an additional embodiment of the invention, the sacrificial structures form a three-dimensional network of metal distributed in brittle oxides; the mesh size of this metal net is designed such that the adhesion between the metals and the brittle oxides is reinforced to avoid delamination.
In the second embodiment of the invention, a slot is opened into the protective overcoat, reaching from the overcoat surface at least to the surface-nearest electrically conductive layer of the composite sacrificial structure, and surrounding the periphery of the chip. This slot stops any crack, which propagates from the dicing line towards the circuitry approximately parallel to the overcoat surface.